1. Field of the Invention
The present invention relates to a multimedia computing system and operating method. More specifically, the present invention relates to an apparatus and technique for queuing messages from a host computer for usage by an accelerator in a multimedia computing system.
2. Description of the Related Art
Multimedia computer systems often include hardware accelerators to improve performance of media displays and other output devices. One common hardware accelerator is a graphics accelerator. A graphics accelerator is a hardware device dedicated to increasing the speed and performance of graphics. Graphics accelerators implement I/O-bound or computation-intensive tasks such as blits, polygons and text rasterization, freeing a central processing unit in a multimedia computer system for other operations.
Graphics accelerators generally include a form of hardware first-in-first-out (FIFO) buffer. Host requests to the accelerator pass through the FIFO. The hardware FIFO is usually small, on the order of 4 to 16 messages in depth. Disadvantageously, a typical FIFO requires that controller controlling the FIFO to perform a side read operation to determine whether the FIFO is full. Often, a host read of an accelerator status register causes pipeline flushing and incurs a wait state, a system overhead which results in a substantial degradation of system performance.
A hardware FIFO is typically implemented either as a plurality of hardware registers within the accelerator or as hard-defined memory elements in a static RAM (SRAM) memory to attain a suitable operating speed. Both hardware registers and SRAM cells consume a relatively large circuit area so that a substantial increase in the number of entries within the FIFO is not desirable from the perspective of cost and circuit size. Furthermore, both hardware registers and dedicated SRAM use circuit space for only the single purpose of message queuing. Due to these size constraints, a typical FIFO in a graphics accelerator has a small capacity so that the queue is often filled and delays are incurred while waiting for available space in a full queue.
Accordingly, in a conventional graphics accelerator, a small FIFO size and substantial overhead incurred to achieve read synchronization severely degrade system performance.